The increasing speed and complexity of today's designs implies a significant increase in the power consumption of very-large-scale integration chips. To meet the power consumption challenge, researchers have developed many different design techniques to reduce power. However, with the complexity of contemporary integrated circuits, having over 100 million transistors, clocked over 1 GHz, manually performing power optimization on chip designs would be hopelessly slow and all too likely to contain errors. Thus computer-aided design tools (CAD) and associated methodologies have become a necessity for designing integrated circuits.
Many different techniques may be used to reduce power consumption at the circuit level. Some of the techniques include transistor sizing, voltage scaling, voltage islands, variable VDD, multiple threshold voltages, power gating, among others. Transistor sizing includes techniques of adjusting the size of each gate or transistor for minimum power. Voltage scaling techniques include lower supply voltages, which use less power, but at the expense of speed. Voltage islands include different blocks that can be run at different voltages, saving power. This design practice, however, may require the use of level-shifters when two blocks with different supply voltages communicate with each other. With variable VDD, the voltage for a single block can be varied during operation—high voltage (and high power) when the block needs to go fast, and low voltage when slow operation is acceptable. Techniques using multiple threshold voltages, in the simplest form, have transistors with two different thresholds available, commonly referred to as High-Vt and Low-Vt, where Vt is the threshold voltage. Generally, high threshold transistors are slower but leak less, and can be used in non-critical circuits. Power gating techniques use high Vt sleep transistors which cut-off a circuit block when the block is not switching, though the sleep transistor sizing may be an important design parameter.
Ideally, these power reduction techniques may be utilized by chip designers on a cell-by-cell basis for an optimum design. However, for circuits with millions of transistors, the structure, timing goal, and design schedule of the circuit greatly limits the designers ability to use the above techniques to achieve potential power savings. Hierarchical schematics/layout can drastically shorten the design cycle of a macro, but offers the fewest opportunities to power detuning algorithms. Timing goals often times converge late (or even post-layout) in a design cycle. Detuning to those goals without introducing schedule risk and layout rework presents a nearly impossible task to the circuit designers.
The above problems are common to most custom or semi-custom designs and rarely have a definitive solution. It is possible to maximize potential power savings in a macro by increasing the granularity of the hierarchy or building it flat. This, however, comes at a cost of increased complexity, schematic/layout entry time, and CAD tool run time. Timing goals for a design are usually met by over designing critical paths to include some amount of padding, intended to insure against late design rework. This, however, introduces extra gate area and wasted power.
Contemporary solutions do not offer a complete solution to the over design problem, though, as they are highly manual and require a specific design structure to be followed. Additionally, contemporary solutions do not address existing or already complete designs. A significant problem facing most circuit designers using the contemporary tools is how to design efficiently, yet still maximize the ability to reclaim wasted power as a post-processing step outside the regular design cycle.